// POH Insert module
module OH_SINS(
   RESET,
   TCLK_155M,

   MPI_TSOH_J0,
   MPI_TSOH_AUAIS,
   MPI_TSOH_K1,
   MPI_TSOH_K2,
   SMON_REI_CNT,
   
   DBIN_TDATA,
   DBIN_FCNT8,
   DBIN_FCNT270,
   DBIN_FCNT9,
   DBIN_MFCNT64,

   DBOUT_TDATA,
   DBOUT_FCNT8,
   DBOUT_FCNT270,
   DBOUT_FCNT9
   );

input              RESET;
input              TCLK_155M;

input[127:0]       MPI_TSOH_J0;
input              MPI_TSOH_AUAIS;
input[7:0]         MPI_TSOH_K1;
input[7:0]         MPI_TSOH_K2;
input[15:0]        SMON_REI_CNT;
   
input[63:0]        DBIN_TDATA;
input[2:0]         DBIN_FCNT8;
input[8:0]         DBIN_FCNT270;
input[3:0]         DBIN_FCNT9;
input[5:0]         DBIN_MFCNT64;

output reg[63:0]   DBOUT_TDATA;
output reg[2:0]    DBOUT_FCNT8;
output reg[8:0]    DBOUT_FCNT270;
output reg[3:0]    DBOUT_FCNT9;

reg[7:0]           SINS_TSOH_J0;
reg[15:0]          SINS_REI_CNT_ME1, SINS_REI_CNT_ME2;
reg[15:0]          SINS_REI;
wire[7:0]          SINS_TSOH_M0, SINS_TSOH_M1;

always @( DBIN_MFCNT64 or MPI_TSOH_J0) begin
   case ( DBIN_MFCNT64[3:0] )
   4'h0:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*0+7:8*0];
   4'h1:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*1+7:8*1];
   4'h2:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*2+7:8*2];
   4'h3:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*3+7:8*3];
   4'h4:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*4+7:8*4];
   4'h5:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*5+7:8*5];
   4'h6:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*6+7:8*6];
   4'h7:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*7+7:8*7];
   4'h8:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*8+7:8*8];
   4'h9:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*9+7:8*9];
   4'hA:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*10+7:8*10];
   4'hB:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*11+7:8*11];
   4'hC:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*12+7:8*12];
   4'hD:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*13+7:8*13];
   4'hE:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*14+7:8*14];
   4'hF:     SINS_TSOH_J0[7:0]   <= MPI_TSOH_J0[8*15+7:8*15];
   default:  SINS_TSOH_J0[7:0]   <= 8'h00;
   endcase
end

always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 ) begin
      SINS_REI_CNT_ME1[15:0]            <= 16'd0;
      SINS_REI_CNT_ME2[15:0]            <= 16'd0;
   end
   else begin
      SINS_REI_CNT_ME1[15:0]            <= SMON_REI_CNT[15:0];
      SINS_REI_CNT_ME2[15:0]            <= SINS_REI_CNT_ME1[15:0];
   end
end
always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 )
      SINS_REI[15:0]                 <= 16'd0;
   else begin
      if ( SINS_REI_CNT_ME1[15:0]==SINS_REI_CNT_ME2[15:0])
         SINS_REI[15:0]              <= SINS_REI_CNT_ME2[15:0];
   end
end
   assign  SINS_TSOH_M0[7:0]  =SINS_REI[15:8];
   assign  SINS_TSOH_M1[7:0]  =SINS_REI[7:0];

always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 )
      DBOUT_TDATA[63:0]            <= 64'd0;
   else begin
      if ( DBIN_FCNT9[3:0]==4'd0 && ( DBIN_FCNT270[8:0]==9'd0 || DBIN_FCNT270[8:0]==9'd1 || DBIN_FCNT270[8:0]==9'd2) ) begin      // A1
         DBOUT_TDATA[63:0]         <= 64'hF6F6F6F6_F6F6F6F6;
      end
      else if ( DBIN_FCNT9[3:0]==4'd0 && ( DBIN_FCNT270[8:0]==9'd3 || DBIN_FCNT270[8:0]==9'd4 || DBIN_FCNT270[8:0]==9'd5)) begin  // A2
         DBOUT_TDATA[63:0]         <= 64'h28282828_28282828;
      end
      else if ( DBIN_FCNT9[3:0]==4'd0 && (DBIN_FCNT270[8:0]==9'd6 || DBIN_FCNT270[8:0]==9'd7 || DBIN_FCNT270[8:0]==9'd8)) begin
         if ( DBIN_FCNT9[3:0]==4'd0 && DBIN_FCNT270[8:0]==9'd6 && DBIN_FCNT8[2:0]==3'd0 )                                         // J0
            DBOUT_TDATA[63:0]      <= {SINS_TSOH_J0[7:0], 56'h555555_55555555};
         else
            DBOUT_TDATA[63:0]      <= 64'h55555555_55555555;                                                                      // un-scramble bits afters J0
      end
      else if ( DBIN_FCNT9[3:0]==4'd3 &&  DBIN_FCNT270[8:0]<9'd9) begin                                                           // AU Point
         if ( DBIN_FCNT270[8:0]==9'd0 && DBIN_FCNT8[2:0]==3'd0 )                                                                  // first H1
            DBOUT_TDATA[63:0]      <= 64'h6A9B9B9B_9B9B9B9B;
         else if ( DBIN_FCNT270[8:0]==9'd1 || DBIN_FCNT270[8:0]==9'd2 || ( DBIN_FCNT270[8:0]==9'd0 && DBIN_FCNT8[2:0]!=3'd0 ) )   // others H1
            DBOUT_TDATA[63:0]      <= 64'h9B9B9B9B_9B9B9B9B;
         else if ( DBIN_FCNT270[8:0]==9'd3 && DBIN_FCNT8[2:0]==3'd0 )                                                             // first H2
            DBOUT_TDATA[63:0]      <= 64'h0AFFFFFF_FFFFFFFF;
         else if ( DBIN_FCNT270[8:0]==9'd4 || DBIN_FCNT270[8:0]==9'd5 || ( DBIN_FCNT270[8:0]==9'd3 && DBIN_FCNT8[2:0]!=3'd0 ) )   // others H2
            DBOUT_TDATA[63:0]      <= 64'hFFFFFFFF_FFFFFFFF;
         else
            DBOUT_TDATA[63:0]      <= 64'd0;                                                                                      // H3
      end
      else if ( DBIN_FCNT9[3:0]==4'd8 && DBIN_FCNT270[8:0]==9'd3 && DBIN_FCNT8[2:0]!=3'd0) begin                                  // M0 M1
            DBOUT_TDATA[63:0]      <= {8'd0, SINS_TSOH_M0[7:0], SINS_TSOH_M1[7:0], 40'd0};
      end
      else begin
            DBOUT_TDATA[63:0]      <= DBIN_TDATA[63:0];
      end
   end
end

always @(posedge RESET or posedge TCLK_155M) begin
   if ( RESET==1'b1 ) begin
      DBOUT_FCNT8[2:0]             <= 3'd0;
      DBOUT_FCNT270[8:0]           <= 9'd0;
      DBOUT_FCNT9[3:0]             <= 4'd0;
   end
   else begin
      DBOUT_FCNT8[2:0]             <= DBIN_FCNT8[2:0];
      DBOUT_FCNT270[8:0]           <= DBIN_FCNT270[8:0];
      DBOUT_FCNT9[3:0]             <= DBIN_FCNT9[3:0];
   end
end

endmodule
